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• CPU configuration

• 1K x 13 bits on-chip ROM
• 32 x8 bits on-chip registers (SRAM, general purpose)
• 5 level stacks for subroutine nesting
• Less than 1.5 mA at 5V/4MHz
• Typically 15μA, at 3V/32kHz
• Typically 1μA, during Sleep mode

• I/O port configuration

• 2 bidirectional I/O ports: P5,P6
• 12 I/O pins
• Wake-up port: P6
• 6 Programmable pull-down I/O pins
• 7 programmable pull-high I/O pins
• 7 programmable open-drain I/O pins
• External interrupt : P60

• Operating voltage range

• 2.3V~5.5V at 0°C~70°C (Commercial Grade)

• Operating frequency range (base on 2 clocks)

• Crystal mode:

DC ~ 20 MHz / 2clks @ 5V

DC ~ 8 MHz / 2clks @ 3V

DC ~ 4 MHz / 2clks @ 2.3V

The transient point of system frequency between HXT and LXT is 400 kHz.

• ERC mode

DC ~ 2 MHz / 2clks @ 2.1V

• IRC mode:

Oscillation mode : 4 / 8 / 1 MHz and 455kHz Process Deviation: Type: Max. ± 3% Temperature Deviation: ± 2% (0 ~ 70°C)

• Peripheral configuration

• 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt
• Power on reset and 3 programmable level voltage reset POR: 1.8V (Default), LVR: 4.0, 3.5, 2.7V
• 2 -/ 4 clocks per instruction cycle selected by code option

• Three Available Interrupts:

• TCC overflow interrupt
• Input-port status changed interrupt (wake-up from sleep mode)
• External interrupt

• Special Features

• Programmable free running watchdog timer
• Power saving Sleep mode
• Selectable Oscillation mode
• Programmable prescaler of oscillator set-up time

• Package type: